GitHub

s-i-r-i/UVM_MUX_2-1

HDL: Verilog HVL: System Verilog TB Methodology: UVM EDA Tools: Questasim Description:- The multiplexer is a combinational circuit that combines multiple inputs into a single output. The multiplexer ...
GitHub

Releases: Velaarjun/2-1-MUX-Implementation-in-Spartan-7-FPGA

You can create a release to package software, along with release notes and links to binary files, for other people to use. Learn more about releases in our docs.
BBC

Positions, directions and turns

What are positions and directions? You can use position words to describe where something or someone is. For example, you can use words such as, 'above', 'below', 'near', 'far', 'up' or 'down'. You ...
IEEE

Design and Implementation of Full Adder using 4 to 1 line Multiplexer Based on Nonlinear Switching Micro Ring Resonator Structure

Abstract: This paper intended to assert the designing of the four to one line multiplexer logic using nonlinear switching techniques based on Micro Ring Resonator (MRR) structure for the proposed full ...
IEEE

Design of 4:1 Multiplexer using Gate Diffusion Input Technique and Comparison of Delay and Power Performance with CMOS Logic

Abstract: The aim of this research is to develop a 4:1 mul-tiplexer using the advanced GDI logic. As compared to CMOS transistor logic, GDI technique reduces the power consumption and propagation ...